Browse Prior Art Database

High Voltage FET Integrated Circuit Process

IP.com Disclosure Number: IPCOM000080083D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Chang, CS: AUTHOR [+2]

Abstract

Monolithic high-voltage field-effect transistors (FETs) suitable for driving gas panels, for example, and characterized by high diffused region-to-substrate breakdown voltage and parasitic FET threshold voltage are fabricated by the following five masking step process. 1) Starting material is 20 ohm-cm P-type silicon wafer (Na ~ 7x10/14/ cm/-3/). 2) 200 angstroms thermal oxide is grown and then 300 angstroms silicon nitride and 1000 angstroms pyrolytic silicon oxide are deposited on the wafer. 3) (First masking step) All device areas within boundaries 1 and 2 are covered with photoresist, as shown in the plan view of Fig. 1 (including channel, source-drain, N-diffusion interconnection, and P-substrate contact). 4) Pyrolytic silicon oxide and silicon nitride are etched away from the nondevice areas.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

High Voltage FET Integrated Circuit Process

Monolithic high-voltage field-effect transistors (FETs) suitable for driving gas panels, for example, and characterized by high diffused region-to-substrate breakdown voltage and parasitic FET threshold voltage are fabricated by the following five masking step process. 1) Starting material is 20 ohm-cm P-type silicon wafer (Na ~ 7x10/14/ cm/-3/). 2) 200 angstroms thermal oxide is grown and then 300 angstroms silicon nitride and 1000 angstroms pyrolytic silicon oxide are deposited on the wafer. 3) (First masking step) All device areas within boundaries 1 and 2 are covered with photoresist, as shown in the plan view of Fig. 1 (including channel, source-drain, N-diffusion interconnection, and P- substrate contact). 4) Pyrolytic silicon oxide and silicon nitride are etched away from the nondevice areas. 5) Boron is diffused through the 200 angstroms thermal oxide in the non-device (field) areas, which then are reoxidized to a thickness of about 8000 angstroms. 6) (Second masking step) Gate areas and P- substrate contact areas within boundaries 3 and 4, respectively, of Fig. 1, are blocked off with photoresist. 7) Phosphorous is ion-implanted in areas 5 and 6 of Fig. 2, using photoresist as an implantation mask for the gate areas and P- substrate contact areas. The field region is masked by the 8000 angstroms oxide 7. 8) The pyrolytic oxide is etched, the photoresist is stripped and the nitride is dip-etched from the phosphorus implantation area, followed by a phosphorus drive-in and reoxidation (1000 angstroms to 6000 angstroms o...