Browse Prior Art Database

Low Power Gated Receiver

IP.com Disclosure Number: IPCOM000080084D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Chin, WB: AUTHOR [+2]

Abstract

This is a low-power, high-performance receiver fabricated from bipolar and complementary metal-oxide silicon (CMOS) devices. It is designed to interface with a relatively low-voltage driver circuit as a buffer and to convert the low voltage to a high voltage to drive CMOS circuits. The inhibit function is also provided.

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Low Power Gated Receiver

This is a low-power, high-performance receiver fabricated from bipolar and complementary metal-oxide silicon (CMOS) devices. It is designed to interface with a relatively low-voltage driver circuit as a buffer and to convert the low voltage to a high voltage to drive CMOS circuits. The inhibit function is also provided.

In the figure, when the GATE line is at 0 volt, the most negative voltage level, all devices are turned off except P-channel (FET) P1, bipolar transistor T2 and Schottky diode D1. In this state, the OUTPUT is clamped at 0 volt and no data can be gated through the receiver. When the GATE line is at V2 volts, the most positive level, N-channel transistors N1 and N2 are turned on and device P1 is turned off, thereby allowing data to be gated into the receiver.

When the DATA line is at 0 volt, and the GATE line is up, bipolar transistor T1 and T2 are off but transistor P2 is on, thereby charging the output line to V2 volts. If the DATA line goes from 0 to V1 volts, which has a value between 0 and V2 volts, bipolar transistor T1 and T2 are turned on, thereby discharging the OUTPUT to ground. P-channel transistor P2 is only slightly turned on at this point, thereby minimizing circuit power dissipation. Because the circuit provides a low impedance, the output line charges and discharges rapidly to assure a high-performance circuit.

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