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"Skip Back" Technique in Test Pattern Elimination

IP.com Disclosure Number: IPCOM000080086D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Storey, TM: AUTHOR

Abstract

This technique more efficiently establishes a desired test pattern sequence by a "pattern sampling" technique.

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"Skip Back" Technique in Test Pattern Elimination

This technique more efficiently establishes a desired test pattern sequence by a "pattern sampling" technique.

Known pattern elimination techniques first find the most difficult fault in a provided file of tests. Once found, the value of the primary inputs at that pattern (referred to as pattern "N" for example) are resimulated to see if the fault previously detected is now detected. If not, pattern "N-1" and "N" are simulated and so on, until the necessary sequence is established. With the advent of LSI circuitry, where sequences of 100-500 patterns are not unusual in the process of detecting failures, with some sequences above 1000 patterns, the above technique is highly time-consuming. For example, assuming a 500 pattern sequence is necessary, this method would simulate 125,250 input changes to establish the sequence.

The presently described technique, "jumps back" a group of patterns and reduces significantly the amount of simulation required.

By the present technique, the most difficult fault is first found. Secondly, the effect of the primary inputs at that pattern (refer to as pattern "N", for example) is simulated. Simulation at this point assures that any purely combinational faults are immediately detected. It also provides a minimum sequence for future simulation.

Thirdly, there is a scan back through the record until either a new fault is encountered or pattern "N-X" is found. "X" is a small positive integer initially a s...