Browse Prior Art Database

Single Device Push Pull Read Only Storage Cell

IP.com Disclosure Number: IPCOM000080087D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Askin, HO: AUTHOR

Abstract

This is an improved one device push-pull read-only storage (ROS) cell.

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Single Device Push Pull Read Only Storage Cell

This is an improved one device push-pull read-only storage (ROS) cell.

It is well known to construct a ROS array in which data bits are stored by single field-effect transistors (FET). Typically, in semiconductor integrated circuit technology, thin oxide is provided under the gate electrodes of operative FETs. If the oxide under the gate electrode is made thicker, an operative FET is not provided even though the source and drain diffusions are formed in their customary manner. Binary "1's" and "0's" are stored depending upon whether a particular data bit position has an operative or an inoperative FET.

By the present technique, the storage of binary 1's and 0's is determined by whether the drain electrode of a single N-channel FET device of the storage cell is connected to a positive potential or ground. Thus, all of the push-pull single- device storage cells 1 to 6 in the figure include operative FETs. A signal on a particular word line (WL) renders the associated FET conductive, providing either an up or a down level all of the push-pull single-device storage cells 1 to 6 in the figure include operative FETs. A signal on a particular word line (WL) renders the associated FET conductive, providing either an up or a down level output on the associated bit line (BL).

The present technique does not use more silicon area than conventional nonpush-pull ROS cells. The present cell has an improved cycle time and simplifies...