Browse Prior Art Database

Bidirectional, High Voltage, MOSFET's

IP.com Disclosure Number: IPCOM000080094D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Fang, FF: AUTHOR [+2]

Abstract

In many applications, such as display drivers, high voltage active devices are required. It is often desirable that the active devices be operated bidirectionally, i.e., source and drain can be used interchangeably. The known techniques to make high-voltage field-effect transistors (FET's) is to use a protective gate at the drain junction to prevent its breakdown, or offset the control gate and lightly implant the channel region near the drain to relax the drain field. Both techniques operate unidirectionally and require a closed-channel structure.

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Bidirectional, High Voltage, MOSFET's

In many applications, such as display drivers, high voltage active devices are required. It is often desirable that the active devices be operated bidirectionally,
i.e., source and drain can be used interchangeably. The known techniques to make high-voltage field-effect transistors (FET's) is to use a protective gate at the drain junction to prevent its breakdown, or offset the control gate and lightly implant the channel region near the drain to relax the drain field. Both techniques operate unidirectionally and require a closed-channel structure.

What is proposed is different structures and methods for high-voltage metal- oxide semiconductor (MOS) FET's, such that the device breakdown voltage of the bulk junction may be achieved in either operational directions.

The devices are open channel and symmetrical with respect to the channel. Both junctions are completely surrounded by field plates and can be alternatively served as control gate or guard rings.

In the configuration of Fig. 1A, an overlapping guard ring structure is illustrated. In Fig. 1A a cross-sectional view is shown. The substrate doping level is chosen such that the breakdown voltage of planar N/+/P junction is the upper limit of the device. Conventional Si-gate technology is employed to form a double-gate structure, with each gate completely surrounding the respective junctions. Metal extension gate on G2 and contacts on SD and G1 are then evaporated, following the opening of the appropriate contact holes. The oxide on poly Si is accompanied by the diffusion drive-in process du...