Browse Prior Art Database

High Density Single Device Memory Cell

IP.com Disclosure Number: IPCOM000080146D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Barson, F: AUTHOR [+5]

Abstract

In this single-device memory cell greater density is achieved because the capacitor is located over the active device, thereby exploiting the vertical dimension of the structure.

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High Density Single Device Memory Cell

In this single-device memory cell greater density is achieved because the capacitor is located over the active device, thereby exploiting the vertical dimension of the structure.

The circuit diagram of the cell indicated in Fig. 1 has a word line 10 connected to a gate electrode 24, a bit/sense line 14 in contact with a diffused region 15, shown in Fig. 5, and a capacitor 16 with one electrode in direct contact with a second diffused region 17. Plates 18 and 19 which comprise the capacitor 16 are located directly over gate electrode 24. Thus, conserving device area.

In the fabrication of the device cell, a thermal SiO(2) layer 20 is formed on P type wafer 22, an opening is formed in layer 20 and the exposed portion of wafer 22 reoxidized to form layer 25. A layer of polysilicon is then deposited and removed except for the gate electrode 24. Openings are made through the underlying thermally oxidized SiO(2) layer 25 and diffused regions 15 and 17 formed. The wafer is subsequently reoxidized forming layer 26 which covers the diffusion windows, as well as the surface of gate electrode 24. Contact openings are then made over region 15 and 17, a second layer of polysilicon is deposited on the surface of the wafer and etched to form stripes 27, capacitor plate 19, and contact 28. A layer 30 of suitable dielectric, e.g. SiO(2), Al(2)O(3) or Si(3)N(4) is then formed over the surface of the wafer and etched to expose stripe 27. A sec...