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Complementary FET Fabrication Utilizing In Situ Pyrolytic Masking Layers

IP.com Disclosure Number: IPCOM000080150D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Chappelow, RE: AUTHOR [+7]

Abstract

Complementary field-effect transistor (FET) processing may be divided into three stages; substrate preparation (wafer processing to form areas for the complementary devices), device fabrication exclusive of gate structure, and lastly, the fabrication of the gate insulator and metallization. The before-mentioned second processing stage is significantly facilitated by the utilization of in situ pyrolytic masking layers comprising silicon nitride, polycrystalline silicon, and pyrolytic oxide.

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Complementary FET Fabrication Utilizing In Situ Pyrolytic Masking Layers

Complementary field-effect transistor (FET) processing may be divided into three stages; substrate preparation (wafer processing to form areas for the complementary devices), device fabrication exclusive of gate structure, and lastly, the fabrication of the gate insulator and metallization. The before- mentioned second processing stage is significantly facilitated by the utilization of in situ pyrolytic masking layers comprising silicon nitride, polycrystalline silicon, and pyrolytic oxide.

N-type silicon substrate 1 of Fig. 1 is processed to produce p pocket 2 in which an N channel FET is to be formed later. Thick oxide 3 is produced and removed in those areas 4 and 5 in which P channel and N channel FETs, respectively, are to be formed. Then, a composite in situ pyrolytic layer is formed over the entire structure. The composite layer is formed in a conventional pyrolytic reactor. First, conditions are established for a standard silicon-nitride deposition. After a time sufficient to grow a thin layer of nitride, the NH(3) is turned off and the silane continues to flow for an additional period sufficient to deposit a thin layer of polycrystalline silicon. Then N(2)O is introduced with the silane for a period sufficient to grow a thin layer of pyrolytic silicon dioxide. The adhesion properties of the individual layers comprising the composite layer are excellent, due to the in situ processing which causes a gradual transition at the interfaces between the polysilicon and the nitride, and between the pyro oxide and the polysilicon.

Now, the first of two photoresist steps is undertaken using conventional techniques. The photoresist pattern is developed and transferred into the pyrolytic oxide layer, to define all those areas which are to be diffused later. Fig. 1 shows the structure resulting at this time.

Next, a second photoresist step is executed to "block out'' the regions to be later P doped. The wafer is then etched in polysilicon etch producing the structure shown in Fig. 2. Vertical surface overetching is substantially eliminated, since the underlying silicon nitride layer is not rapidly affected by the polysi...