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Fabricating Complementary Semiconductor Devices

IP.com Disclosure Number: IPCOM000080151D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 90K

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR [+2]

Abstract

In this method which utilizes masks for forming diffusion windows for opposite type impurities, dip etching and mask alignment problems are minimized.

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Fabricating Complementary Semiconductor Devices

In this method which utilizes masks for forming diffusion windows for opposite type impurities, dip etching and mask alignment problems are minimized.

In generally practiced semiconductor fabrication techniques, isolation regions are formed between subcollector regions prior to epitaxial deposition. Because the subcollector must be of low resistivity and isolation must out-diffuse into the epitaxial layer and be of sufficiently high concentration to prevent inversion, both subcollector and isolation diffusions must have a high-surface concentration. Therefore, to prevent low collector to isolation breakdown voltages, subcollector and isolation must be sufficiently spaced so that when they diffuse sideways they do not intersect at high concentration. This limits the spacing between the subcollectors.

In practicing this process, a triple layer diffusion mask consisting of a first layer 10 of pyrolytic SiO , an overlying second layer 12 of Si(3)N(4), and a third layer 14 of pyrolytic SiO(2) is deposited by conventional techniques on an N- substrate 15, as shown in Fig. 1. Conventional photolithographic techniques are used to form diffusion window 16 in the triple dielectric layer. Region 19 can be formed by conventional diffusion techniques, as shown in Fig. 2, by depositing a layer of P-doped oxide, or ion implantation. After the diffusion is made, a drive-in step is necessary to enlarge the region 19.

Subsequently, depending on the method used to introduce the impurity, a layer 18 of th...