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Triple Density MNOS Memory Array with Field Shield

IP.com Disclosure Number: IPCOM000080160D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Krick, PJ: AUTHOR

Abstract

A high density metal nitride oxide semiconductor (MNOS) memory array may be fabricated in a manner which produces a new structure, which differs from the conventional MNOS array in several important respects. Instead of etching individual holes in the field oxide to form the gate region of each of the MNOS devices, a single hole running the length of a bit line is etched in the field oxide. In this hole, 20A of silicon dioxide is grown and the remainder of the array is covered by a thick field oxide (5000 to 10,000 angstroms thick). In addition, high density is further enhanced by the use of alternating aluminum and polysilicon word lines, which are arranged orthogonally to the bit lines. For example, all even numbered word lines in an array may be aluminum while the odd numbered word lines may be polycrystalline silicon.

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Triple Density MNOS Memory Array with Field Shield

A high density metal nitride oxide semiconductor (MNOS) memory array may be fabricated in a manner which produces a new structure, which differs from the conventional MNOS array in several important respects. Instead of etching individual holes in the field oxide to form the gate region of each of the MNOS devices, a single hole running the length of a bit line is etched in the field oxide. In this hole, 20A of silicon dioxide is grown and the remainder of the array is covered by a thick field oxide (5000 to 10,000 angstroms thick). In addition, high density is further enhanced by the use of alternating aluminum and polysilicon word lines, which are arranged orthogonally to the bit lines. For example, all even numbered word lines in an array may be aluminum while the odd numbered word lines may be polycrystalline silicon.

An outline of the fabrication procedure for such a structure is given in what follows starting with a source-drain diffusion step. Up to that point, the processing is the same as for a conventional MNOS array structure. 1. Source and Drain Diffusion (n+). 2. Etch the gate regions of the fixed (decoder and control devices)

and variable-threshold devices. 3. Grow thick oxide (300 angstroms) for the fixed-threshold devices. 4. Etch the gate regions of the variable-threshold memory devices. 5. Grow 20 angstroms SiO(2). 6. Deposit Si(3)N(4) over wafer (500 angstroms). 7. Deposit poly-Si for odd numbered word lines. 8. Etch poly-Si. 9. Grow 6000 angstroms SiO(2) on the poly-Si word lines.
10. Open contact holes.
11. Deposit Al.
12. Etch Al.

The increase in density for the structure resulting from the above-outlined process is due to the fact that the spacing between word lines is not determined by photolithographic constraints, but by the thickness of the silicon dioxide grown on the polycrystalline silicon in step 9. This reduces the spacing between word lines considerably. The close spacing of word lines should cause no fringing field problems, because the separation between the word lines is an order of magnitude greater than the gate insulator thickness. The density is further increased because the word lines in this structure can be the minimum allowable line width; no side overlap of metal over the gate region is required, because of the long thin gate insulator region. Although the resulting structure requires one additional masking step because of the two types of word lines, no critical alignment is required for these since a field-effect transistor (FET) is formed whenever a word line intersects the thin oxide region.

By changing one masking step in the above-outlined process, the triple- density MNOS memory array can be converted into an array of similar density

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with a field shield over all parasitic devices in the array. Parasitic devices are formed whenever a word line crosses over two diffusions and a thick insulator exists between the silic...