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Width To Length Ratio Design Program for Interacting Dynamic FET Circuits

IP.com Disclosure Number: IPCOM000080170D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Brechling, GE: AUTHOR [+6]

Abstract

This program provides width-to-length ratios for dynamic field-effect transistor (FET) circuits prior to formation in a semiconductor. An iterative process combines physical models of interacting dynamic FET circuits to meet a required performance specification, for minimum device size and desired performance.

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Width To Length Ratio Design Program for Interacting Dynamic FET Circuits

This program provides width-to-length ratios for dynamic field-effect transistor (FET) circuits prior to formation in a semiconductor. An iterative process combines physical models of interacting dynamic FET circuits to meet a required performance specification, for minimum device size and desired performance.

Each circuit is physically characterized by a width-to-length ratio for a driven load. Calculating the load for each circuit permits a width-to-length ratio to be chosen for the circuit driving the load. Iteratively calculating the load for each circuit in a combination of circuits incorporates the interacting affects among the circuits. The load capacitances indicates whether or not a minimum capacitance exist for a circuit to operate properly. The lack of a minimum capacitance indicates when capacitance padding is required to achieve proper operation for a circuit, as well as for the combination of circuits.

As an operation 10, the program is initialized by supplying the following inputs for each circuit:
a) Load Factors - two sets of load factors are provided for each

tree in each circuit to be formed in the semiconductor.

Load factors may be calculated by hand or by a separate

program. One load factor corresponds to the external

capacitance which can be driven by the circuit.

The second load factor corresponds to the total capacitance,

including the circuits output capacitance which can be

driven. For a complex circuit with more than one tree, a

separate load factor must be determined for each distinct

tree. Two trees within a single circuit are considered

distinct if their load factors are different.
b) Wiring capacitance is calculated by hand or by a program for

each circuit tree.
c) Maximum width-to-length ratio specification is entered for

each tree. The specification guarantees convergence of the

program.
d) Minimum stepping increment is entered for increasing and

rounding up a width-to-length ratio.
e) Maximum number of iterations the program will permit before

terminating.
f) Truncation constant is minimum change in width-to-length ratio

which, when not exceeded by any circuit, will be interpreted by

the program as convergence and will cause the program to

terminate.
g) The number of distinct width-to-length ratios to be

determined is entered.
h) A master logic list is entered which describes the input and

output connections for each device.

As an operation 12 a counter N, initialized in the operation 10, is incremented for the first program iteration and each successive iteration thereafter.

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An operation 14 calculates the fan-out capacitance for each circuit based on c...