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Field Effect Transistor Circuit Discharge Analysis Program

IP.com Disclosure Number: IPCOM000080171D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Love, RD: AUTHOR [+2]

Abstract

Complex dynamic field-effect transistor (FET) logic circuits may be designed and evaluated based on the discharge characteristic of their FET devices. This program analyzes trees of FET devices stacked to any height for node voltages, currents and other parameters.

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Field Effect Transistor Circuit Discharge Analysis Program

Complex dynamic field-effect transistor (FET) logic circuits may be designed and evaluated based on the discharge characteristic of their FET devices. This program analyzes trees of FET devices stacked to any height for node voltages, currents and other parameters.

Fig. 1 shows a typical FET device 10 in a stack of "L" devices. The equation describing current flow through each device is given by:

(Image Omitted)

Since there are both L nodes and L devices, all variables are treated as a programming vector of length L, i.e., V(GS), WLR, GMA/node. The program iteratively transfers charge from a capacitor at node `n' to the capacitor at node `n+1' (for all n </- L) during a time interval dt. Node voltages are computed for each interval dt until T = TMAX, where T = time incremented by the program, and TMAX = maximum time specified by the designer.

In Fig. 2, as a first operation 12 a designer provides the program the number of FET devices in the stack. An operation 14 adjusts the capacitive loading (C, C1, C2) of each device in the stack. The operation is adapted to enter a 0 at those nodes of the device where the external capacitive loading is insignificant. An operation 16 enters the transconductance (GMA) and width-to-length ratio (WLR) for each device in the stack. The operation is adapted to provide the same programming vector quantities for those parameters that are entered as scaler quantities. The capacitances C3 and C4 are calculated from formulae 5 and 6 (Fig. 1) in an operation 18. The internal node voltages at each device may be specified by the designer. Alternatively, an operation 20 sets the internal node voltages to a level corresponding to a precharge level (assuming all devices have the output voltage VI on their respective gates during precharge). This is the typical worst-case conditi...