Browse Prior Art Database

Destination Checking of Memory Arrays

IP.com Disclosure Number: IPCOM000080183D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Howe, LD: AUTHOR [+2]

Abstract

Memory arrays used with CPU's have never been totally checked. The arrangement of Fig. 1 checks data and address failures. In previous array checking mechanisms, the destination register, the address and the byte marks are normally checked at the input of the array before or during destination time. Then a write operation (destination) occurs, immediately followed by a read operation using the same identical address. This latter read operation is commonly called a "flush thru check". Data that was just destined into the stack is read out and compared to the destination register to verify that all bits were properly destined.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 61% of the total text.

Page 1 of 2

Destination Checking of Memory Arrays

Memory arrays used with CPU's have never been totally checked. The arrangement of Fig. 1 checks data and address failures. In previous array checking mechanisms, the destination register, the address and the byte marks are normally checked at the input of the array before or during destination time. Then a write operation (destination) occurs, immediately followed by a read operation using the same identical address. This latter read operation is commonly called a "flush thru check". Data that was just destined into the stack is read out and compared to the destination register to verify that all bits were properly destined.

In the IBM 3145 processor, two arrays kept the same information and at destination time were "flush thu" and "compare" checked. This is a good check for a cell failure in the array, but does not check address, address decode, and address bus failures within the array package itself. These failures will cause new data to be written into the wrong area, thus causing undetectable and/or unretryable errors.

Fig. 1 shows a circuit that checks for address failures during the destination period. It should be noted that there are two arrays 1 and 2 storing identical data in a dual-rail data flow. The destination address is applied to decode circuits 3, 4 of the arrays 1, 2 and a read, a write, and another read operation are executed in sequence as shown in Fig. 2. The first read cycle reads the old data at the de...