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Digital Delay Circuit

IP.com Disclosure Number: IPCOM000080203D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Kuckein, PA: AUTHOR

Abstract

This circuit replaces a single-shot and offers lower cost, more reliability and accuracy in those applications where appropriate timing signals are available.

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Digital Delay Circuit

This circuit replaces a single-shot and offers lower cost, more reliability and accuracy in those applications where appropriate timing signals are available.

The basic circuit is implemented with flip-flops which trigger on positive gate transitions. Flip-flop 1 changes state with the first positive clock transition after the gate control goes negative, conditioning gate 3 via inverter 4. Flip-flop 2 changes state with the next positive clock transition after flip-flop 1 changes state and conditions gate 5. This occurs time T after the gate falls where T < T < 2 tau where tau is the clock period. This represents a delay of nominal period 1.5 tau +/-0.5 tau. This variation of +/- 33% of nominal period is comparable to the variation in timing of conventional single-shots made with standard components.

When the gate control is brought positive, both triggers are reset and the circuit is immediately ready to begin timing again. This is an improvement over conventional single-shots which require substantial reset times before initiation of the next cycle, to avoid inaccuracy of timing.

Additional delay may be gained by cascading additional stages comprising a gate and a flip-flop connected as is gate 5 and flip-flop 2. Each additional stage will add a delay of tau and will hot contribute to the variation. Since the amount of variation is +/-0.5 tau, the accuracy of the delay increases as more stages are added resulting in a nominal period of (1....