Browse Prior Art Database

Bit Inversion Compensation Logic for Shift Registers and Memory Arrays

IP.com Disclosure Number: IPCOM000080205D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Miller, RW: AUTHOR [+3]

Abstract

Certain integrated circuit memory cell designs require special refresh cycles to maintain data. These refresh cycles also invert the polarity of the data. The logic circuit shown compensates for this inversion and permits correct operation of the shift register or array, independent of the number of refresh cycles.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 74% of the total text.

Page 1 of 2

Bit Inversion Compensation Logic for Shift Registers and Memory Arrays

Certain integrated circuit memory cell designs require special refresh cycles to maintain data. These refresh cycles also invert the polarity of the data. The logic circuit shown compensates for this inversion and permits correct operation of the shift register or array, independent of the number of refresh cycles.

The total contents of the memory is maintained in either true or complemented form. When in true form, input data is stored in true form and output data leaves in true form. When the memory is in complemented form, the input data is complemented when stored and the output data is recomplemented to restore it to true form. Thus, the input and output are always in true form, regardless of the true or complement state of the memory. The state of the memory is maintained in a binary toggle which complements on each inverting cycle. The input and output complementing is done using "exclusive-OR" circuits as inverters 1 and 3 controlled by the flip-flop 4.

To allow integration of the compensation logic with the shift register 2, the flip-flop 4 has a design similar to a stage of the shift register. To insure that flip- flop 4 is refreshed at proper intervals, both the shift and refresh signals are 0Red by 0R 5 to complement and refresh flip-flop 4. Thus, flip-flop 4 is refreshed at the same rate as the shift register cells of shift register 2.

In the prior art, every other bit in the shif...