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Binary Full Subtractor

IP.com Disclosure Number: IPCOM000080207D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Poole, AL: AUTHOR

Abstract

Fig. 1 shows a binary full subtractor comprising a series of cascade subtractor stages 1, 2, 3 and 4.

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Binary Full Subtractor

Fig. 1 shows a binary full subtractor comprising a series of cascade subtractor stages 1, 2, 3 and 4.

Fig. 2 shows the logic in each subtractor stage and the logic statement for each logic block.

Fig. 3 shows a truth table for the subtractor stage of Fig. 2.

As can be seen from Fig. 1, the subtractor stages can be cascaded. to form a subtractor in the same manner as previous adder stages have been cascaded to form adders. It should be noted that the carry output F2 of the highest order stage must be connected to the carry input C of the lower order stage. If there is a carry output from the highest order stage, the subtrahend was larger than the minuend. Under this condition, the output of the subtractor will be the complement of the difference. Circuitry is provided to complement the output of the subtractor stages in this case, to provide a true binary indication of the difference between the two numbers, and also by raising a sign bit indicating that the answer is a negative number.

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