Browse Prior Art Database

Digital Noninteger Divider

IP.com Disclosure Number: IPCOM000080210D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Chapman, TA: AUTHOR

Abstract

A digital circuit which produces a noninteger frequency division of a master clock frequency is shown. The circuit utilizes two counters, 10 and 14, that divide by a chosen odd ratio n, which operate off positive transitions of the clock pulses 12 coming from phase splitter 22. A value n-1 over 2 is set into counter 10, and the value 0 is set into the second counter 14. It must be insured that the master clock is gated so that the first pulse entering phase splitter 22 is a positive going pulse. This results in counter 10 being incremented 1/2 pulse before counter 14. The two counter outputs are now 180 degrees out of phase and are ORed together, resulting in the output signal 20 at the desired frequency n/2.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Digital Noninteger Divider

A digital circuit which produces a noninteger frequency division of a master clock frequency is shown. The circuit utilizes two counters, 10 and 14, that divide by a chosen odd ratio n, which operate off positive transitions of the clock pulses 12 coming from phase splitter 22. A value n-1 over 2 is set into counter 10, and the value 0 is set into the second counter 14. It must be insured that the master clock is gated so that the first pulse entering phase splitter 22 is a positive going pulse. This results in counter 10 being incremented 1/2 pulse before counter 14. The two counter outputs are now 180 degrees out of phase and are ORed together, resulting in the output signal 20 at the desired frequency n/2.

For example, to produce a division of 7 1/2, the first counter 10 produces an output which is a division of 15 of the frequency of the pulses produced by master clock 12. The second counter 14 likewise produces a division of 15 at its output. The outputs of the two counters are combined in OR circuit 16. Counter 10 and 14 are designed so that a signal on external reset line 18 causes 10 to be set to "7" and counter 14 to be set to "0". The output at terminal 20 represents a division by 7-1/2 of the master clock frequency.

1

Page 2 of 2

2

[This page contains 1 picture or other non-text object]