Browse Prior Art Database

Multiprocessor Interface

IP.com Disclosure Number: IPCOM000080222D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Boehner, WE: AUTHOR [+4]

Abstract

The drawing depicts a multiprocessor data processing system including two or more central processing units (CPU) 1. Each processor includes a storage control unit 2, which includes necessary controls to implement a buffer backing store technique for utilization of a high-speed buffer 3, and also includes a storage protect key array 4 in accordance with IBM System/360 or System/370 storage protect mechanisms. Each of the CPU's and storage control units share data from a shared storage device 5. To be described is the interface required between the two processors to coordinate various aspects of high-speed buffer operation, modification of storage protect keys, and reconfiguration of the entire data processing system.

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Multiprocessor Interface

The drawing depicts a multiprocessor data processing system including two or more central processing units (CPU) 1. Each processor includes a storage control unit 2, which includes necessary controls to implement a buffer backing store technique for utilization of a high-speed buffer 3, and also includes a storage protect key array 4 in accordance with IBM System/360 or System/370 storage protect mechanisms. Each of the CPU's and storage control units share data from a shared storage device 5. To be described is the interface required between the two processors to coordinate various aspects of high-speed buffer operation, modification of storage protect keys, and reconfiguration of the entire data processing system.

The lines associated with only one processor will be described, but it is understood that each processor in a multiprocessor system will have the same capabilities. Since each CPU 1 must communicate with all of storage and because each CPU 1 has a high-speed buffer 3, it is necessary to take special steps to insure that the copy of data in the buffer 3 is in fact a valid current copy. Whenever a CPU 1 stores data, address information on line 6 is transferred to the shared storage 5 along with the data to be stored on a line 7. The address information is used in high-speed buffer 3 on line 8 to determine whether or not the data being modified also is in the high-speed buffer 3, in which case the data will be used to update the high-speed buffer on a line 9.

To insure that the high-speed buffer 3 of any other processor utilizes most current value of data, the fact of storing data on line 7 is utilized to gate address information on line 10 to the high-speed bu...