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High Reliability Dynamic Switching of Data Transfer Path and Circuits

IP.com Disclosure Number: IPCOM000080227D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Blum, AR: AUTHOR [+3]

Abstract

The data processing system shown consists of several processors PR1 to PRn which are linked with I/O units via a dynamic I/O bus, microprogram controlled switching networks, control units CUl to CUn, loop adapters LA1 to LAn, and loops L1 to Ln.

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High Reliability Dynamic Switching of Data Transfer Path and Circuits

The data processing system shown consists of several processors PR1 to PRn which are linked with I/O units via a dynamic I/O bus, microprogram controlled switching networks, control units CUl to CUn, loop adapters LA1 to LAn, and loops L1 to Ln.

Each compressor PR comprises a switch, ensuring that a connection exists to an I/O bus line not occupied by the other processors on the dynamic I/O bus. To this end, the switches are locked against each other. For example, if processor PRl becomes defective, the dynamic I/O bus permits processor PRn to replace the defective processor in full. In order to further improve the flexibility of the data processing system and to ensure that a defective control unit or a loop adapter is readily replaced, switching networks are arranged both between the dynamic I/O bus and the control units CU, which may be designed as front ends, and between control units CU and loop adapter LA. These networks ensure that if a control unit, a front end or a loop adapter fails, another corresponding circuit not occupied at the time fully replaces the defective circuit. A suitable unoccupied circuit is chosen via the associated switching network, which is controlled by the microprogram of the data processing system.

Loops L1 to Ln are linked with loop adapters LA1 to LAn. As previously mentioned, these loops are capable of servicing several I/O units. In order to replace one of t...