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Browse Prior Art Database

Field Shield MOS Transistor with Self Aligned Gate

IP.com Disclosure Number: IPCOM000080230D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Kroell, KE: AUTHOR [+2]

Abstract

To permit metal oxide semiconductor (M0S) transistor memories to be readily produced, N-channel field-effect transistors (FET's) are used. Care must be taken that the gate overlap capacities are as low as possible.

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Field Shield MOS Transistor with Self Aligned Gate

To permit metal oxide semiconductor (M0S) transistor memories to be readily produced, N-channel field-effect transistors (FET's) are used. Care must be taken that the gate overlap capacities are as low as possible.

The surface inversion risk inherent in N-channel FET structures as a result of (positive) oxide loads is eliminated by a conductive polysilicon field shield, connected to the substrate potential, being arranged above the semiconductor arrangement outside the gate areas. A minimum gate overlap capacity is ensured by the use of self aligned gate technologies.

The figure shows such a FET structure. P- semiconductor substrate comprises N+ doped source and drain regions 2 and 3, respectively. The semiconductor substrate is covered by a double layer 4, 5 of SiO(2) and Si(3)N(4), respectively. Outside the channel region, this is followed by relatively thick layer 6 of conductive polysilicon which serves as a field shield. To isolate conductive polysilicon layer 6 against gate electrode 7, the field shield is coated with a further SiO(2) layer 8. There is no connecting metallization of the source and drain regions 2 and 3. In many cases these regions are connected in the semiconductor substrate direct by highly doped N+ conductor paths.

In the arrangement shown in the left part of the figure, shorts beween gate metal 7 and conductive polysilicon layer 6 may occur at the point marked by arrow 9. These shorts or...