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Internal Wrap Test for Microprogrammed Binary Synchronous Communications Adapter

IP.com Disclosure Number: IPCOM000080231D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Houdek, ME: AUTHOR [+3]

Abstract

This internal wrap test allows microprogrammed control unit (MPU) 10 to initiate a check of the binary synchronous communications adapter (BSCA) on BSCA circuit module 11, before any communication is attempted. The majority of the logic required for the wrap test is incorporated in BSCA circuit module 11.

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Internal Wrap Test for Microprogrammed Binary Synchronous Communications Adapter

This internal wrap test allows microprogrammed control unit (MPU) 10 to initiate a check of the binary synchronous communications adapter (BSCA) on BSCA circuit module 11, before any communication is attempted. The majority of the logic required for the wrap test is incorporated in BSCA circuit module 11.

The microprogram test routine is retained in read-only storage and executed automatically each time the operator selects communications mode. Any errors detected during the internal wrap test inhibit communication.

MPU 10 conditions BSCA circuit module 11 by turning on the test mode bit, line 12. This also causes transmit data line 13 to be wrapped back into the received data line 14. MPU 10 loads a SYN character (hexidecimal 32) into data register 15, which the BSCA then gates into shift register 19 and begins shifting. MPU 10 then turns on NEW SYNC line 17 to reset the SYN character latches 18. When the SYN character is shifted halfway through shift register 19, the BSCA gates back a hexidecimal 23. The BSCA continues to shift the SYN character until it has been decoded twice and the SYN character latches 18 are set. When the SYN character latches 18 are set, the BSCA gates back the hexidecimal 32. By this sequence of functions shift register 19, transmit data trigger 20, receive data trigger 21, SYN character decodes latches 18, gating circuits and timing (which constitute about...