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High Speed Input/Output Delay Counter

IP.com Disclosure Number: IPCOM000080236D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Swearingen, KW: AUTHOR [+2]

Abstract

This high speed input/output (I/O) delay counter provides-delay functions for I/O controllers, which are triggered by asynchronous signals from attached I/O devices. The delay counter is particularly advantageous in that all delays are microprogrammed, preloaded and can be easily changed by changing the microroutine which performs the counter load function.

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High Speed Input/Output Delay Counter

This high speed input/output (I/O) delay counter provides-delay functions for I/O controllers, which are triggered by asynchronous signals from attached I/O devices. The delay counter is particularly advantageous in that all delays are microprogrammed, preloaded and can be easily changed by changing the microroutine which performs the counter load function.

The high speed I/0 delay counter is initialized by transferring halfwords of data from a host controller, not shown, via the programmed I/O (PIO) bus 10 into input data register 15. The two high-order bits of register 15, i.e., bits 0 and 1 are control bits and determine whether data is written into or read from buffer 30. Bits 2-7 of register 15 feed into a 6-bit compare circuit 16 and define the buffer address for the reading or writing operation.

Address counter 25, which is being incremented by free-running oscillator 24, also feeds 6 bits into compare circuit 16 and when the value in counter 25 is equal to the value of bits 2-7 from register 15, compare circuit 16 provides an output. Further, when bit 0 of register 15 is a 1 and an address compare from 16 occurs, bits 8-15 of register 15 are written into the high byte of buffer 30 and 0's are written into the low byte. lf bit 1 of register 15 is a 1 and an address compare occurs, then the contents of the data buffer 30 at the address in counter 25 is loaded into output register 50. If both bits 0 and 1 of register 15 are 1 and an address compare occurs, the contents of the buffer is loaded into output register 50 before the buffer is written into as previously described.

The output of compare circuit 16 feeds AND circuit 17 and inverter 18 which control gates 19 and 20, respectively, which in turn control the entry of data into the high and low bytes of buffer 30. The entry of data into register 50 is controlled by AND circuit 49. AND circuit 49 is controlled by the output of compare 16 and by a gating signal, in a marner similar to the control of AND circuit 17.

The length of data buffer 30 is equal to the maximum value of address counter 25. Hence, if address counter 25 has a value of 2, it is addressing the second halfword buffer in data buffer 30. For each counter value there is also associated a count control latch. Count control latches 40 are set under control of AND circuits 41, which are conditioned by asynchronous external signals or by other count control latches. The important thing to note is that when any particular count control latch is set, its time out function is enabled. Further, each time counter 25 is incremented, a halfword of data is read from the addressed buffer position and is available at the buffer output until the next address increment occurs.

The high-byte output, i.e., bit 0-7 from buffer 30 leads into compare circuit 31 and the low byte, i.e., bits 8-15 feeds into incrementor circuit 32. Incrementor 32 is reset under control of AND circuits 33 and OR c...