Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Digital Phase Control for Ink Jet Printing

IP.com Disclosure Number: IPCOM000080245D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Jackson, FE: AUTHOR

Abstract

The continuous, unlimited and completely digital control of the phasing of the charge plate voltage in an ink jet printer is provided by the system depicted in Fig. 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 61% of the total text.

Page 1 of 2

Digital Phase Control for Ink Jet Printing

The continuous, unlimited and completely digital control of the phasing of the charge plate voltage in an ink jet printer is provided by the system depicted in Fig. 1.

Charged ink drops 10 are directed towards split gutter 11. Gutter 11 is positioned such that if an ink drop is charged with a voltage V1, (see Fig. 3), the drop will enter the lower half of gutter 11, and if the drop is charged to a voltage V2, it will enter the upper half of gutter 11.

Eight signals of the same frequency as the printer head excitation, but displaced in time as shown in Fig. 2, are generated by a phase generator, not shown. These signals are connected to data selector 17. The technique used is to select the two closest signals, one of which will place all the ink drops in the upper half of gutter 11, and the other of which will place all the ink drops in the lower half of gutter 11. The break off point, i.e., the part where ink drops break free of the ink stream leaving the head, is then situated between the two signals selected.

Initially, data selector 17 gates the signal phase 0 to the charge plates. If this signal directs any ink to the lower half of gutter 11, the sensor 12 and detector 13 will respond and the sample hold circuit will store the signal generated. Counter 16 is an up/down counter, with the output of sample hold circuit 14 controlling the direction of the count. At the sample time, which is generated by sample time gener...