Browse Prior Art Database

Process for Interconnection Metallization

IP.com Disclosure Number: IPCOM000080258D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Sharma, V: AUTHOR

Abstract

An interconnection metallization process that permits larger target areas and avoids mismatch pads on integrated circuits while improving reliability is described.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Process for Interconnection Metallization

An interconnection metallization process that permits larger target areas and avoids mismatch pads on integrated circuits while improving reliability is described.

The usual steps in creating an integrated circuit, up to and including the formation of conductive lines on the surface of the semiconductor wafer are followed. 0nce the conductive lines interconnecting the devices on the wafer have been formed, the circuits are masked so that only termination lands which provide for connecting the circuit to the exterior world are exposed. Layers of chrome-copper and gold are then evaporated on these termination lands.

Once this metallice layer is evaporated on the lands the mask is removed, and a coating of an insulation polyamide is applied over the wafer surface and the polyamide cured. The cured polyamide coating is then masked and the coated termination lands exposed, by etching the polyamide coating in an alkaline solution. The exposed termination are then coated with lead-tin solder and reflowed.

By using this process sputtered quartz can be eliminated and the halo effects after reflow are diminished to increase process yields.

1