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Self Gating High Speed Metal Oxide Semiconductor Decoder

IP.com Disclosure Number: IPCOM000080262D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Hockedy, RS: AUTHOR

Abstract

An internally timed decoder circuit which puts a small load on true complement generators driving it and which requires a minimum number of word lines is described.

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Self Gating High Speed Metal Oxide Semiconductor Decoder

An internally timed decoder circuit which puts a small load on true complement generators driving it and which requires a minimum number of word lines is described.

The decoder is arranged such that its input transistors are connected in common to a field-effect transistor (FET), whose gate is driven by a NAND gate. The NAND gate which has as its inputs a pair of true complement inputs, so that the common point of connection of the input transistors will remain high until all the true complement generators have assumed their proper state.

In the figure suitable true complement generators, not shown, drive 16 decoder circuits of which only one is shown. The true complement signals drive the gates of decoder transistors T1 through T4. The sources of these transistors are connected in common to node A, which fans out to the other 15 decoders. In standby, the input phi 1 to the gate transistor T7 is low holding transistor T7 off. Simultaneously inputs E1 and E1 are high keeping transistors T8 and T9 on. Thus the gate of transistor T10 is at ground and transistor T10 is off.

When pulse phi 2 turns on transistor T5, the capacitor C is precharged and the gate of transistor T6 is bootstrapped when phi 3 rises. Transistor T5 is held off isolating the decoder from the precharged capacitor C1.

When a memory cycle begins, phi 1 rises and the true complement inputs E1, E1, E2, E2, E3, E3, E4, and E4 assume their proper...