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Testing Field Effect Transistor Modules

IP.com Disclosure Number: IPCOM000080264D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Campbell, AH: AUTHOR [+5]

Abstract

An N-channel field-effect transistor (FET) device 10 has protective diode 11 connected between a chip substrate 12 through a diffused resistor 13 to an input pad 14. Various AC capacitive coupled FET gates, e.g., gate 15, are structured in device 10 for connection through diffused resistor 13 to input pad 14.

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Testing Field Effect Transistor Modules

An N-channel field-effect transistor (FET) device 10 has protective diode 11 connected between a chip substrate 12 through a diffused resistor 13 to an input pad 14. Various AC capacitive coupled FET gates, e.g., gate 15, are structured in device 10 for connection through diffused resistor 13 to input pad 14.

During the manufacturing and associated device testing, assembly into circuit cards and card test, and subsequent handling during life, stresses such as electrical transients, electrostatic discharges, etc., may occur at the device input. These stresses may have increased the device input leakage, although not necessarily to a level which may affect the correct operation of the device in its circuit application. A leakage test of the protective diode 11 is, therefore, a basis for determining whether the device 10 has been subjected to an excessive stress.

The leakage test is performed by applying a negative DC potential 16 volts to the chip substrate, a negative potential of 11 volts to the device ground, and measuring the input leakage circuit with ammeter 16 if necessary. In summary, leakage testing after assembly on a continuing basis can indicate electrical stresses have occured.

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