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Shared/Distributed Discharge Devices

IP.com Disclosure Number: IPCOM000080273D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Finger, WC: AUTHOR [+7]

Abstract

A dynamic logic field-effect transistor (FET) circuit comprises: a power cell such as FET devices 11, 13, and 15 for precharging an output node, a logic cell such as FET devices 17 and 19 for setting up conditional discharge paths, and a discharge cell such as FET device 21 for conditionally discharging the output node. In those circuit layout designs where several dynamic logic circuits operate during the same phase times and are physically close to each other, circuit chip area can be saved by sharing a larger discharge cell between two or more circuits. Circuits 10 and 30 of the figure are shown to share discharge device 21.

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Shared/Distributed Discharge Devices

A dynamic logic field-effect transistor (FET) circuit comprises: a power cell such as FET devices 11, 13, and 15 for precharging an output node, a logic cell such as FET devices 17 and 19 for setting up conditional discharge paths, and a discharge cell such as FET device 21 for conditionally discharging the output node. In those circuit layout designs where several dynamic logic circuits operate during the same phase times and are physically close to each other, circuit chip area can be saved by sharing a larger discharge cell between two or more circuits. Circuits 10 and 30 of the figure are shown to share discharge device 21.

In those circuit layout designs where a dynamic logic circuit includes a logic cell having various branches being driven from remote areas of an integrated circuit chip, area used for diffused or metallized conductor paths can be saved by duplicating the discharge cell, and distributing these duplicates to areas where the logic cell branches are located. The discharge cell associated with circuit 40 has been duplicated in form of FET 51 serving logic cell branch devices 47 and 49 and FET 61 serving logic cell branch devices 57 and 59.

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