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Single Clock Shift Register Latch

IP.com Disclosure Number: IPCOM000080288D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Williams, TW: AUTHOR

Abstract

In the conventional design of sequential control of double-latch circuits, two timing clocks are usually necessary. One of the problems associated with having two clocks for a device such as a shift register latch is the inherent skew. To avoid this problem, a double-latch circuit is shown which uses a single-clock source. All logic blocks in this circuit are "AND INVERT".

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Single Clock Shift Register Latch

In the conventional design of sequential control of double-latch circuits, two timing clocks are usually necessary. One of the problems associated with having two clocks for a device such as a shift register latch is the inherent skew. To avoid this problem, a double-latch circuit is shown which uses a single-clock source. All logic blocks in this circuit are "AND INVERT".

In the figure, the double-latch circuit consists of a polarity hold latch I followed by a set-reset latch II. Latch I is supplied at its clock input with a conventional clock pulse train. Input data is supplied at the data terminal. In operation, both latches are set by the same clock pulse. In particular, latch I sets when the clock pulse is making a positive going transition. Latch II sets when the clock pulse is making a negative going transition. This design eliminates the inherent skew between two clock pulse sources by using the same clock. This technique can also be used with a standard shift register so that one clock can control the even and odd shift positions.

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