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Output Latch for Memory Array

IP.com Disclosure Number: IPCOM000080293D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Hsieh, JC: AUTHOR

Abstract

This is a high performance output latch circuit requiring no gating pulse and implemented in complementary metal oxide silicon (CMOS) technology.

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Output Latch for Memory Array

This is a high performance output latch circuit requiring no gating pulse and implemented in complementary metal oxide silicon (CMOS) technology.

As shown in the figure, the input to the circuit is received at either read common bit sense line (B/SO) or read common bit sense line (B/S1). The P channel field-effect transistor devices are designated as P1 to P5, while the N channel field-effect transistor devices are designated as N1 to N4. During a write operation, both input lines are at an up level (+V) maintaining devices P1, P5 and P4 off. N4 being an N channel device is turned on, bringing the common node between N4 and P5 to a down level (ground) maintaining transistor N3 off. The output is thereby maintained at the level of node B, which is determined by the state of the latch consisting of transistors N1, N2, P2 and P3.

In order to read data out, assume first that node B is at an up level (logic 0 level). This requires node A to be at a down level. If next the common bit line B/S1 is brought to a down level, devices P1 and P5 are turned on while device N4 is turned off. This in turn turns on device N3 discharging node B to ground level. This down level is indicative of a logic "1" level at the output node. If a logic "0" level has been provided for read out than bit line B/S0 would have been brought to a down level, while bit line B/S1 was maintained at an up level. This would turn transistor P4 on, bringing node B to an up le...