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Browse Prior Art Database

Testing Site for Determining Capacitances of Integrated Circuits

IP.com Disclosure Number: IPCOM000080305D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Chang, AW: AUTHOR

Abstract

In the fabrication of integrated circuits, it is important to be able to accurately determine the capacitances between isolation regions and active regions in the integrated circuits enclosed by such isolation regions. Because the nature of isolation regions has become increasingly complex and it is difficult to separate the stray capacitance encountered in the measurement, more sophisticated structures are required to determine such capacitances and their components.

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Testing Site for Determining Capacitances of Integrated Circuits

In the fabrication of integrated circuits, it is important to be able to accurately determine the capacitances between isolation regions and active regions in the integrated circuits enclosed by such isolation regions. Because the nature of isolation regions has become increasingly complex and it is difficult to separate the stray capacitance encountered in the measurement, more sophisticated structures are required to determine such capacitances and their components.

Since such complex isolation structures often involve the combination of different types of isolation, such as the combination of junction isolation and recessed oxide dielectric isolation, in many structures it is, in addition, desirable to have a test structure which is capable of determining the effect on capacitances and breakdown voltages of several structural contributors to the overall isolation.

The present structure, as shown in the figures, accomplishes such functions. Fig. 1 shows the test structure design. The vertical structure may be similar to a transistor region, N-type resistor region or epitaxial resistor pocket. The contributors of pocket capacitance may be separated, as due to "sidewall" and due to the "floor". A capacitor equation can be used for the device as follows: C(d) = C(s) + C(f) = 1C(s1) + aC(f1) where

C(d) = Total device capacitance.

C(s) = Total sidewall capacitance.

C(f) = Total floor capacitance.

1 = D...