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Masking Technique for Diffusion Operation

IP.com Disclosure Number: IPCOM000080307D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Klepner, SP: AUTHOR [+2]

Abstract

This process provides for forming emitter, base and collector openings with a single mask and subsequently retaining a diffusion mask over the base opening, which can be later removed by a dip etching process.

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Masking Technique for Diffusion Operation

This process provides for forming emitter, base and collector openings with a single mask and subsequently retaining a diffusion mask over the base opening, which can be later removed by a dip etching process.

As shown in Fig. 1, a layer 10 of Si0 is deposited on semiconductor wafer 12 having a base region 14 therein. The subcollector region and isolation region are not illustrated in the interest of clarity. Emitter opening 16, base opening 18 and collector opening 20 are formed in layer 10, using a single mask and conventional photolithographic and etching techniques.

As shown in Fig. 2, a blanket layer 22 of Si(3)N(4) is deposited on the surface of semiconductor body 12 over layer 10. An SiO(2) layer 24, preferably deposited pyrolytically at a relatively low temperature, is then deposited over layer 22.

As shown in Fig. 3, a plug consisting of layers 22 and 24 is retained over base contact opening 18. Layer 24 is formed by photolithographic and etching techniques. Layer 24 is then used as an etchant mask to etch Si(3)N(4) layer 22. As indicated in Fig. 3, the forming of the base contact plug does not require a critical alignment masking step. The top layer 24 of the plug is then removed by a dip etching operation. If low-temperature pyrolytic oxide is used, it etches four to five times faster than the underlying thermal oxide layer 10. At this point, the wafer is then subjected to diffusion forming the emitter and coll...