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Complementary Metal Oxide Semiconductor Device

IP.com Disclosure Number: IPCOM000080309D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

James, RP: AUTHOR

Abstract

The complementary metal-oxide semiconductor device is formed by diffusing an impurity region 10 into a P- substrate 12, as shown in Fig. 1. Subsequently, an N- epitaxial layer 14 is deposited on the surface of body 12 over diffused region 10, as shown in Fig. 2. Layer 16 of Si(3)N(4) is formed on the surface of layer 14 and a grid-like opening 18 formed by conventional photolithographic etching techniques.

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Complementary Metal Oxide Semiconductor Device

The complementary metal-oxide semiconductor device is formed by diffusing an impurity region 10 into a P- substrate 12, as shown in Fig. 1. Subsequently, an N- epitaxial layer 14 is deposited on the surface of body 12 over diffused region 10, as shown in Fig. 2. Layer 16 of Si(3)N(4) is formed on the surface of layer 14 and a grid-like opening 18 formed by conventional photolithographic etching techniques.

The exposed regions in opening 18 are then oxidized, until the oxide regions 20 contact the PN junction between layer 14 and semiconductor body 12. Conventional masking and diffusion techniques are used to form P+ source and drain regions 21 and 22 and N+ source and drain regions 24 and 26. The P channel device 28 operates in the usual accepted manner. The N channel device 30 is turned off by causing a depletion region to extend through the epitaxial layer 14.

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