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Medium Speed Multiply

IP.com Disclosure Number: IPCOM000080333D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Larson, RH: AUTHOR

Abstract

For a small to medium size computer that does multiply, the choice is often between either the simple algorithm of add-and-shift-right-one or dedicated hardware that can retire multiple bits in one cycle. There is an intermediate option that can speed up operation.

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Medium Speed Multiply

For a small to medium size computer that does multiply, the choice is often between either the simple algorithm of add-and-shift-right-one or dedicated hardware that can retire multiple bits in one cycle. There is an intermediate option that can speed up operation.

Assuming an ALU with a 32-bit adder and the ability to add and shift in one cycle, the following hardware is added. From a static register that holds the multiplicand, adjacent 4-bit digits are AND-ORed together. Each digit output is wired to a pair of monolithic array logic (MAL) modules. A common 4-bit bus that carries a stream of multiplier digits is fed to all MAL modules. The MAL outputs are wired to one side of an adder that has a conditional shift right four in the loop from the adder output, to a register holding the partial products on the other side of the adder. After each shift, the four bits shifted out are a completed product digit. After the final non-0 multiplier digit is retired, the adder output has the remaining high-order product.

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