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Pulse Sequence Detector

IP.com Disclosure Number: IPCOM000080339D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Henry, DL: AUTHOR

Abstract

The purpose of this circuit is to detect the presence of "n" or more consecutive clock times of input "up level", or "n" or more consecutive clock times of input "down level", and provide an output to indicate the existence of either condition. It can be used in a delta-modulation system having a system clock, not shown, providing significance to "n".

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Pulse Sequence Detector

The purpose of this circuit is to detect the presence of "n" or more consecutive clock times of input "up level", or "n" or more consecutive clock times of input "down level", and provide an output to indicate the existence of either condition. It can be used in a delta-modulation system having a system clock, not shown, providing significance to "n".

The circuit consists of an RC timer, two current switches "A", "B" with collector dotting, two reset circuits "A", "B", and a voltage reference circuit. The voltage reference circuit, not shown, provides two reference voltages, VC and VD, that are chosen such that VC > 1/2 VCC plus one diode drop and VD < 1/2 VCC minus one diode drop. Typical voltage might be VC = +5.0 V and VD = +3.0 V when VCC = +8.0 V.

Assume at the outset that VB = 1/2 VCC. Under this condition, VC > VB > VD so that Q2 and Q5 are on and Q1 and Q6 are off, leaving V out at an "up" level. Assume that slightly thereafter input VA makes a transition to the up level. This turns on Q8 which turns off Q7. This also turns off Q4 and allows Q3 to act as a diode, which charges VB to one base-emitter voltage drop below VC. VB continues to charge at a rate determined by VA, R1 and C1 until VB becomes greater than VC, which turns on Q1 and pulls the output to a "down" level. V out will now remain down as long as VA remains up.

Assuming that VA stays up, the timing is chosen such that the output switches down after "n" but before "n +...