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Analog Pulse Sequence Detector

IP.com Disclosure Number: IPCOM000080340D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Henry, DL: AUTHOR

Abstract

This circuit detects the presence of an "up" level of at least a predetermined duration or "down" level of at least that duration, and provides an output indicating such a condition. Circuits of this kind are useful in delta-modulation devices.

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Analog Pulse Sequence Detector

This circuit detects the presence of an "up" level of at least a predetermined duration or "down" level of at least that duration, and provides an output indicating such a condition. Circuits of this kind are useful in delta-modulation devices.

Q1 and Q4 act as data input gates. Q2, Q3 are reset devices, and Q5, Q6 along with Q7, Q8, Q9 form a two-input OR gate with a threshold voltage level set at point C. Q10, Q11 provide output level shifting and also provide gain for a fast output transition.

Assume phi is up and hence phi down. Phi up saturates Q1 and with R3, R4 << R1, R2, points A and D are both approximately V(SATQ1) above ground. Q4 and Q3 are off since phi is down. Q2 is off since, although its base is one V(BE) above ground, its emitter, which is tied to point E, will be above ground. C1 now is charged through the path R2, C1, R3, Q1, thus allowing point E to rise. E is also the input to Q5 of the OR gate. With both D and E below the referenced voltage at point C, Q11 is on.

As soon as E reaches and exceeds C, the output device, Q11, is turned off. The time constant R2, C1 determines the amount of time required for the output to switch, and is chosen such that the output will switch only after the desired number of clock periods of an associated system, not shown, has elapsed. Any data transition before this time will reset the detector and start the timing over.

Assume now that the data phi has remained up for more than the required number of pulses and, therefore, Q11 is off, and that phi now switches down and phi switches up. E is still at a positively charged level so that Q2 remains off. Q1 is turned off by phi, thus preventing C1 from further charging. Phi coming up starts to turn on Q4. Q4...