Browse Prior Art Database

Inverter Commutating Network

IP.com Disclosure Number: IPCOM000080343D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Felton, BC: AUTHOR [+2]

Abstract

This inverter utilizes silicon-controlled rectifiers to chop DC in push-pull fashion for converting the DC into AC pulses. The operation of the inverter is fully controlled so that the spacing and width of the pulses can be determined, as desired.

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Inverter Commutating Network

This inverter utilizes silicon-controlled rectifiers to chop DC in push-pull fashion for converting the DC into AC pulses. The operation of the inverter is fully controlled so that the spacing and width of the pulses can be determined, as desired.

The inverter utilizes an output transformer 10 having a primary winding with end terminals 11 and 13, and center-tap terminal 15. Terminal 15 is connected to the positive pole of a DC supply E, not shown, and terminal 17 is connected to the negative pole, ground. Current is admitted to the primary winding alternately from terminals 15 to 11 through transistors Q1 and Q3 to 17, and from 15 to 13, through transistors Q2 and Q4 to 17. Conduction in either of these two paths is initiated by a signal to the gates of transistors Q1, Q3 or Q2, Q4 from control 70. The commutate nodes for these two circuits are 31 and 33, respectively.

If Q1, Q3 are conducting, the potential at terminal 11 falls toward ground, and that of terminal 13 rises toward 2E. Commutating capacitor 35 is charged through 51, 53, 37 and Q3.

To turn off path Q1-Q3, 70 fires Q4, which conducts by the power of 35, through the series resonant circuit 35, 37, 39. Inductors 37 and 39 are linked by the same core. Before this current reaches its peak, it reaches the value of the current through Q1; in otherwords, it supplies all of the current previously conducted by Q3, and Q3 becomes back biased and shuts off, and 41 becomes forward b...