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Clock Synchronization for Counting Asynchronous Time Intervals

IP.com Disclosure Number: IPCOM000080352D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Boinodiris, S: AUTHOR

Abstract

Accuracy of asynchronous time interval measurement by clock pulse counting is improved by phase splitting the clock pulses, and counting clock pulses occurring on the phase most nearly coincident with the asynchronous interval initiation. The clock pulse counting is synchronized to within a preselected fraction of the clock pulse duration. A common clock with a relatively fixed frequency controls the generation of multiple clock signals, each of which has a preselected fraction of phase shift relative to the common clock. Decision-making logic selects the most convenient clock for counting with the least amount of time lag between the asynchronous input pulse and the start of a new full count.

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Clock Synchronization for Counting Asynchronous Time Intervals

Accuracy of asynchronous time interval measurement by clock pulse counting is improved by phase splitting the clock pulses, and counting clock pulses occurring on the phase most nearly coincident with the asynchronous interval initiation. The clock pulse counting is synchronized to within a preselected fraction of the clock pulse duration. A common clock with a relatively fixed frequency controls the generation of multiple clock signals, each of which has a preselected fraction of phase shift relative to the common clock. Decision- making logic selects the most convenient clock for counting with the least amount of time lag between the asynchronous input pulse and the start of a new full count.

The Fig. 1 clock synchronization circuitry consists of four major sections; a clock phase splitter 11, a logical latching array, a decoder 40 and a clock pulse selection circuit 50. Clock 10 introduces a waveform of period T (Fig. 2B) to clock phase splitter circuit 11 which, through well-known circuit element combinations (i.e.: inverters and delay elements), transforms the pulses from splitter 10 into N different clocking waveforms 12 - 17 where N is a whole integer. Each of 12 - 17 has a phase shift of the same leading or lagging direction from the last clock pulse, with a quantity equal to Mi multiplied by T and divided by N. Mi is a sequential positive integer from one to N. The last clock in this case has zero phase shift.

The latching array contains N/2 latches (21 - 23 in Fig. 1), which are cross- latched through disabling AND gates 31 - 34 when any one of the latches 21 - 23 is set. Input pulse 20, the asynchronous pulse to be converted to a digital count, is shown as Fig. 2A. The inputs for latches 21 - 23 are an AND function of pulse 20 and the clocking waveforms 12 - 16 delayed by (Mj x T) /N, where Mj equals odd or even (but not both) positive integers from one to N. Figs. 2B, C and D show the case of N = 4. Decoder 40 receives the set outputs of the N/2 latches and decodes the various conditions of latching into 2*N/2 various output lines 41 - 45. Lines 41 - 45 depict the possibilities of pulse 20 timing with respect to each of the clocking waveforms delayed by (Mj x T)/N. Each configuration of outputs 41 - 45 from decoder 40 pinpoints when the input pulse 20 arrived to within a time interval of 2 x T/N.

Clock selector logic 50 selects the closest clock start...