Browse Prior Art Database

Event Controller Useful for Analog Signal Handling

IP.com Disclosure Number: IPCOM000080355D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Boinodiris, S: AUTHOR

Abstract

Counter circuitry used during analog-to-digital conversions (ADC) is effectively timeshared by logic which controls various signal handling functions, other than those directly involved in the analog signal conversion. The circuitry is particularly useful in conjunction with multiple ramp analog-to-digital systems such as that shown in the January 1963 IBM Technical Disclosure Bulletin (Vol. 5 No. 8) at pages 51 - 52 in the article entitled "Analog-to-Digital Converter" by Propster, as well as in U. S. patents 3,577,140 by Aasnaes and 3,733,600 by Hellwarth et al.

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Event Controller Useful for Analog Signal Handling

Counter circuitry used during analog-to-digital conversions (ADC) is effectively timeshared by logic which controls various signal handling functions, other than those directly involved in the analog signal conversion. The circuitry is particularly useful in conjunction with multiple ramp analog-to-digital systems such as that shown in the January 1963 IBM Technical Disclosure Bulletin (Vol. 5 No. 8) at pages 51 - 52 in the article entitled "Analog-to-Digital Converter" by Propster, as well as in U. S. patents 3,577,140 by Aasnaes and 3,733,600 by Hellwarth et al.

A multiple bit counter 10 which is essentially the same as that used in the prior ADC systems, is incremented under control of either event decoder 11 or ADC controls 12. When decoder 11 receives a start signal such as from a controlling processor, it initially generates an enabling signal to gate 13 via 0R 14 so that clock 15 will begin incrementing counter 10. Decoder 11 then responds to the contents of counter 10 to provide sequential event control prior to, during and subsequent to an ADC cycle. For example, decoder 11 can produce a series of output signals on lines 16 - 19 to perform certain preconversion functions in response to the start signal.

Lines 16 set multiplexer block switches and point switches 21, so as to introduce any one of the analog input signals present at input terminals shown generally at 22. Note that 16 can be more than one line for control of block and point selecting. Output 17 closes and opens shorting switch 23 across the input to discharge any capacitance. This is followed by output 18 to cause sample and hold circuit 25 to acquire the signal to be converted, if a sample and hold circuit is used. Output 19 can be used to set the gain of variable-gain amplifier 26 and could be operated in conjunction with gain decision logic, such as that shown in patent 3,754,240 by Milton.

Other functions can be performed by properly sequenced output signals from decoder 11, such as zero...