Browse Prior Art Database

Processor Clock Control System

IP.com Disclosure Number: IPCOM000080377D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Bullions, RJ: AUTHOR [+4]

Abstract

The clocking system described provides for various modes of operation that are required in a data processing system during normal operation, testing of engineering hardware models, and field maintenance.

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Processor Clock Control System

The clocking system described provides for various modes of operation that are required in a data processing system during normal operation, testing of engineering hardware models, and field maintenance.

The clocking control system is utilized to provide two clocks, one identified as an L clock and the other as a T clock shown in Fig. 1a. The L clock is utilized to set latches which reflect the output of data processing system combinational logic. After a delay Y, the T clock is utilized to set a trigger directly connected to the latch. The output of the trigger is then utilized as the input to the next set of combinational logic in the data processing system. Fig. la depicts the normal operation of the clock control system, in which the Y delay between the setting of latches and triggers produces an L/T overlap during each cycle of operation.

Other alternate forms of clock control are shown in Fig. 1b through 1f and include, respectively: normal rate with frequency biasing which permits small changes in cycle time, while preserving the relationship between L and T clocks including the L/T overlap (1b); half rate-short path which allows cycling at one half the normal cycle rate for logic paths, while maintaining the L/T overlap (1c); half rate-long path breaks the L/T overlap while maintaining the T to L relationship, which mode can be used for Scan In or Scan Out of data in accordance with testing techniques (1d); quarter rate, which c...