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Range Check of an Address Counter

IP.com Disclosure Number: IPCOM000080378D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Enger, TA: AUTHOR

Abstract

Some data processing systems provide a form of storage protection, wherein references to storage are constrained to lie within a block of storage locations specified by a lower bound address and an upper bound address. The upper bound address and lower bound address are normally stored in hardware registers in the central processing unit, and each access to storage requires that the address be examined to insure that the address is within the address specified by the upper bound address register and lower bound address register. To be described, is a technique which reduces the time and/or hardware required to perform the check of the upper bound address.

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Range Check of an Address Counter

Some data processing systems provide a form of storage protection, wherein references to storage are constrained to lie within a block of storage locations specified by a lower bound address and an upper bound address. The upper bound address and lower bound address are normally stored in hardware registers in the central processing unit, and each access to storage requires that the address be examined to insure that the address is within the address specified by the upper bound address register and lower bound address register. To be described, is a technique which reduces the time and/or hardware required to perform the check of the upper bound address.

In the drawing, an upper bound address register 1 and lower bound address register 2 are loaded with address information, specifying a lower and an upper bound address within a storage device 3. This information is normally loaded in the registers 1 and 2 prior to initiating access for a particular program, and constrains the program to access data within the bound specified. If addresses are to be accessed in the storage device 3 in sequence, as by an address counter 4, it would normally be required to compare the contents of the counter 4 with the information in registers 1 and 2 prior to each access. Prior to initiating the first access, the address counter 4 will be compared with the contents of the lower bound address register 2 in a compare circuit 5, to insure that the initial access is within the bound specified by the lower bound address.

Normally, each access initiated by the address counter 4 would also be required to be compared with the contents of the upper bound register 1, to insure that the counter has not been incremented past the upper bound address specified.

The necessity for making the co...