Browse Prior Art Database

Phase Locked Oscillator Compensation Circuit

IP.com Disclosure Number: IPCOM000080381D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Gindi, AM: AUTHOR

Abstract

Many systems include a multiplicity of devices that must be precisely synchronized to each other. To this end, a phase-locked oscillator (PLO) control circuit is used to provide a synchronized master clock, in response to the leading edges of reference sync bits applied to the circuit. The PLO incorporates a phase discriminator 10, voltage-controlled oscillator (VCO) 12 and divider 14 in a closed-feedback loop, and includes means for detecting out-of-sync conditions in a detection circuit 16; or missing synchronizing bits in a detection circuit 18.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 90% of the total text.

Page 1 of 2

Phase Locked Oscillator Compensation Circuit

Many systems include a multiplicity of devices that must be precisely synchronized to each other. To this end, a phase-locked oscillator (PLO) control circuit is used to provide a synchronized master clock, in response to the leading edges of reference sync bits applied to the circuit. The PLO incorporates a phase discriminator 10, voltage-controlled oscillator (VCO) 12 and divider 14 in a closed-feedback loop, and includes means for detecting out-of-sync conditions in a detection circuit 16; or missing synchronizing bits in a detection circuit 18.

When an out-of-sync condition is found during the initial or resync periods, a wide window is generated in a window control 20 to gate the referenced sync bits into the phase discriminator 10. On the other hand, during normal operation in the in-sync condition, a narrow window is used. To compensate for the erroneous correction due to missing sync bits, two different compensating signals are developed, namely a short signal to compensate for small error when the narrow window is used, and a longer signal to be used with the wide window.

The reset control 22 controls the timing of the divider counter 14, which provides a signal that is compared to the incoming reference sync bits. The error signal from the phase discriminator is applied through an OR gate 24, or directly to an integrating circuit in the VCO 12, to either increase or decrease the frequency of the timing signal...