Browse Prior Art Database

Variable Cycle Length Clock with Realtime Length Control

IP.com Disclosure Number: IPCOM000080394D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Zurla, FA: AUTHOR

Abstract

The data processing system shown in Fig. 1 has the ability to vary the processor cycle length not only by microcode, but also by realtime needs within the system. The system extends the length of the cycle, depending upon conditions encountered during the microword execution itself and also repeats part of that cycle when necessary. Depending upon the structure of the data flow, it will usually take different amounts of time to execute various functions. If the execution time of all function can be predicted, then an efficient wag of execution is to decode the microinstruction being done and vary the clock cycle to the proper length for that particular operation, e.g., that shown in U. S. Patent No. 3,656,123.

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Variable Cycle Length Clock with Realtime Length Control

The data processing system shown in Fig. 1 has the ability to vary the processor cycle length not only by microcode, but also by realtime needs within the system. The system extends the length of the cycle, depending upon conditions encountered during the microword execution itself and also repeats part of that cycle when necessary. Depending upon the structure of the data flow, it will usually take different amounts of time to execute various functions.

If the execution time of all function can be predicted, then an efficient wag of execution is to decode the microinstruction being done and vary the clock cycle to the proper length for that particular operation, e.g., that shown in U. S. Patent No. 3,656,123. A problem occurs when the same identical function can operate at several speeds, depending upon the physical state of the machine at the time the particular function is being executed. The problem is compounded when the physical conditions that determine the length of the operation cannot be determined, until the cycle has already been partially executed.

The variable-clocking scheme shown in Fig. 2 has the ability to alter its cycle length at any time during the cycle. It accomplishes this end in two different ways to take care of problems that might occur, due to the fact that the cycle has been partially executed before the decision to extend can be made.

Fig. 1 is one example of a system in which the storage word can vary in the above-mentioned manner. A solid-state semiconductor storage is shown in three levels 1, 2 and 3. Level 1 (L1) is a lower density, high-speed array capable of 120ns cycle. Whenever a page of data is accessed, it will be placed in the L1 array so that subsequent operations on it can occur at the fastest possible speed.

When a page not in L1 is addressed, then level 2 (L2) must be accessed (200 ns cycle) to determine Whether or not it holds the data. If it does, the data is then paged down into L1 and also sent t...