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# High Speed Conversion between Binary and Decimal

IP.com Disclosure Number: IPCOM000080406D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 41K

IBM

## Related People

Larson, RH: AUTHOR

## Abstract

A standard algorithm for conversion from one base to another uses repeated divides of the old number. The divisor is the new base, arithmetic is done in the old base, and remainders (which are concatenated to form the new number) are expressed in the new base.

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High Speed Conversion between Binary and Decimal

A standard algorithm for conversion from one base to another uses repeated divides of the old number. The divisor is the new base, arithmetic is done in the old base, and remainders (which are concatenated to form the new number) are expressed in the new base.

A divide unit may be constructed of array logic (MAL) that has, as inputs, two digits of dividend and, as outputs, one digit of quotient and one of remainder. Assuming MAL with four outputs that are arbitrary functions of eight inputs, the units could be as shown in Fig. 1. Note that the low-order bit is not transformed and that, for a decimal-to-hexadecimal conversion (CVB) the remainder is expressed in hexadecimal form.

The steps of a single divide unit transforming two digits per cycle is shown below, as it would do a CVB of the decimal number 516906 to hexadecimal 07E32A. In the following table, the horizontal lines are beneath the two digits which comprise a partial dividend. The two digits below each horizontal line are the quotient and remainder digits.

Improved speed may be obtained by using a second divide unit which lags behind the first by two digits. The steps of such an implementation doing the same CVB are shown below.

Additional speed improvement may be obtained by overlapping three units. The steps for CVB and for conversion back to decimal (CVD) are shown below. Because of the reciprocal nature of the process, the CVB and CVD are mirror image...