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Dual Speed Multiply Unit

IP.com Disclosure Number: IPCOM000080407D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Larson, RH: AUTHOR

Abstract

In dedicated high-speed multiply units customarily supplied with large computers, a cost/performance decision is made on the width of the unit to be implemented. Typically an intermediate width between the widest and narrowest factors ("width" referring to the number of bits in a factor) is selected. Larger factors are broken into manageable size pieces and multiple passes taken. Smaller ones are padded with 0 and leave a portion of the hardware essentially unused. The previously unused portion may be used to speed up multiplication of narrow factors at a modest increase in complexity.

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Dual Speed Multiply Unit

In dedicated high-speed multiply units customarily supplied with large computers, a cost/performance decision is made on the width of the unit to be implemented. Typically an intermediate width between the widest and narrowest factors ("width" referring to the number of bits in a factor) is selected. Larger factors are broken into manageable size pieces and multiple passes taken. Smaller ones are padded with 0 and leave a portion of the hardware essentially unused. The previously unused portion may be used to speed up multiplication of narrow factors at a modest increase in complexity.

In a typical unit one of the factors, call it the multiplicand, is held fixed for the duration of the operation. The other factor, the multiplier, is broken into groups of bits that, as they are presented to the unit, cause numbers representing a multiple of the multiplicand to be entered into the adder where the partial product circulates, shifting with each add cycle to receive the new multiple in the proper position. As the completed product spills off the low-order end it is assembled into final form.

If the multiply unit is two or more times the width of a multiplicand then two or more multiplications can take place simultaneously, if certain changes are made to prevent interference. Two of the simplest schemes are illustrated by a decimal example with six-digit factors on hardware with twelve-digit width, capable of retiring one digit per cycle.

Both...