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Isolation Scheme for Line Terminated Logic

IP.com Disclosure Number: IPCOM000080421D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Fang, FF: AUTHOR [+2]

Abstract

The basic gate of the terminated line logic is shown in Fig. 1. A gate current, I, has to be supplied to each logic gate. It is convenient to consider all such gates sharing the same supply current; all gates connected in series (Fig. 2). This interconnection of logic gates has to be designed to satisfy two main criteria: 1) It should provide adequate isolation between gates; and 2) It should allow relatively rapid resetting of gates by taking I to and from zero.

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Isolation Scheme for Line Terminated Logic

The basic gate of the terminated line logic is shown in Fig. 1. A gate current, I, has to be supplied to each logic gate. It is convenient to consider all such gates sharing the same supply current; all gates connected in series (Fig. 2). This interconnection of logic gates has to be designed to satisfy two main criteria: 1) It should provide adequate isolation between gates; and 2) It should allow relatively rapid resetting of gates by taking I to and from zero.

A compromise solution, between the requirements of 1) and 2), obtained using only passive elements (the ratio of Z(s) to Z(o) and the relative lengths of these transmission lines) is generally unacceptable for reasons of speed and/or margins.

Using an additional Josephson gate per logic gate allows switching between two configurations of gate supply, to obtain a more satisfactory solution to the requirements of 1) and 2). Consider the circuit of Fig. 3.

The isolation gate is denoted by J2 and is controlled via the control line C1. To establish the gate current, I, C1 is activated to ensure that the maximum supercurrent of the isolation gate J2 is relatively low. I(m) << I.

Under these conditions the isolation gate presents a resistive-capacitance load to the gate supply line (Fig. 4). The gate supply line of characteristic impedance Z(s) can be considered in a lumped approximation as an inductance L(s), and the output lines as a lumped capacitance C(out).

The ri...