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NOR/OR Circuit

IP.com Disclosure Number: IPCOM000080442D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Vogl, NG: AUTHOR

Abstract

This field-effect transistor (FET) logic circuit provides either true or false logic levels on a single output terminal, in response to input data and a control signal. In certain classes of memories, it is desirable to have a decoder which has only one output positive at selection time (NOR function) for certain operations, and to have all outputs positive except one (OR function) for other operations.

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NOR/OR Circuit

This field-effect transistor (FET) logic circuit provides either true or false logic levels on a single output terminal, in response to input data and a control signal. In certain classes of memories, it is desirable to have a decoder which has only one output positive at selection time (NOR function) for certain operations, and to have all outputs positive except one (OR function) for other operations.

The circuit is divided into two functional areas, a logic section and a control section. The logic section includes a plurality of typical logic circuits such as, for example, logic gates 10 including load device Q1 and gating devices Q2, Q3, and Q4. Utilizing N-channel FET devices, when node N1 is positive with respect to node N2, the circuit will operate as a conventional NOR circuit. If the potentials are reversed, N1 negative with respect to N2, the circuits operate as source follower OR circuits. In the NOR mode, one and only one output is positive for a unique combination of input signals A, B, and C, for example, as required in a decoder circuit for memory operation. In the OR mode all outputs are positive except one. The input lines labeled A, B, C, etc. are supplied by conventional true-complement drivers.

A control section of the circuit provides the proper bias to nodes N1 and N2, depending on the condition of the control signal input. The potential for node N1 is provided by the inverter pair Q5 and Q6 which provides a positive potential...