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Metal Oxide Silicon Capacitance Voltage Measurement System

IP.com Disclosure Number: IPCOM000080447D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Forslund, D: AUTHOR

Abstract

The quality of the dielectric of metal-oxide semiconductor (MOS) gates is ascertained ultimately by measurements of capacitance and voltage. Flat-band voltage, flat-band capacitance, dielectric thickness, substrate doping, maximum (minimum) capacitance, capacitance vs voltage response and leakage characteristics are derived from these measurements. Fig. 1 depicts a system which automatically measures capacitance and voltage, and then analyzes and reports the corresponding dielectric quality.

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Metal Oxide Silicon Capacitance Voltage Measurement System

The quality of the dielectric of metal-oxide semiconductor (MOS) gates is ascertained ultimately by measurements of capacitance and voltage. Flat-band voltage, flat-band capacitance, dielectric thickness, substrate doping, maximum (minimum) capacitance, capacitance vs voltage response and leakage characteristics are derived from these measurements. Fig. 1 depicts a system which automatically measures capacitance and voltage, and then analyzes and reports the corresponding dielectric quality.

A control wafer 1 is placed in a test fixture. Probe 2 contacts a standard capacitance test site 3. Data acquisition control 4 causes voltage source 5 to apply a chosen series of voltages to the test site 3, via current limiting resistor 6. A digital voltmeter 7 measures the test site voltage. Simultaneously, the test site capacitance is measured by a digital capacitance bridge 8. The series of drive voltage, measured voltage, and measured capacitance values are stored in file 9 via data acquisition 4.

Subsequently, the measured voltage data is smoothed with averaging techniques by control 10, and test site breakdown and leakage W is determined by computation 21 as shown in Fig. 4.

For the negative excursions of the chosen series of applied voltages, the measured voltage Vm is summed. The applied voltage Va is also summed. The wafer leakage resistance W is then determined. The wafer leakage resistance is similarly determined for positive excursions. By summation, error due to external noise sources are reduced. Results are placed in file 9. The measured capacitance data is smoothed in fault resolution section 12. The maximum and minimum responses are further smoothed in section 13, whose process is depicted in Figs. 2 and 3.

Fig. 2 shows the logic necessary to smooth the maxi...