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Browse Prior Art Database

Gated Inverter using Complementary Metal Oxide Silicon Transistors

IP.com Disclosure Number: IPCOM000080450D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Chin, W: AUTHOR [+2]

Abstract

It is generally difficult to tie together two or more outputs of complementary metal-oxide-silicon (CMOS) logic gates to form a dotted OR circuit. The output of the standard CMOS inverter exhibits a low impedance in both the down and the up levels; thus one inverter may act as an additional current path for the output of another inverter circuit. The gated inverter 10 shown in the figure solves this problem, and permits the dotting of two or more outputs without DC power dissipation.

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Gated Inverter using Complementary Metal Oxide Silicon Transistors

It is generally difficult to tie together two or more outputs of complementary metal-oxide-silicon (CMOS) logic gates to form a dotted OR circuit. The output of the standard CMOS inverter exhibits a low impedance in both the down and the up levels; thus one inverter may act as an additional current path for the output of another inverter circuit. The gated inverter 10 shown in the figure solves this problem, and permits the dotting of two or more outputs without DC power dissipation.

A pulse C1 received on the control input is transmitted to the gate of transistor N3 and also to the gate of transistor P2, through the inverter formed by transistors P1 and N1. With the control pulse C1 at a down level, both devices N3 and P2 are turned off; and pulse A1 at the Data input can be transmitted to the output through the inverter comprising devices P3-N2, only when the Control pulse C1 is at an up level. Thus, with a down level at Control input C1, there is a high output impedance from circuit 10, permitting a circuit with an up level Control input such as C2 or C3 to dominate the output. A necessary condition to operation is that only one Control input C1, C2 or C3 may be at an up level during a particular cycle.

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