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Switching Speed Control in Digital Circuits

IP.com Disclosure Number: IPCOM000080459D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 32K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+2]

Abstract

The switching time in digital circuits can be represented as a function of the power supplied, i.e., the higher the circuit speed required, the higher this power has to be.

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Switching Speed Control in Digital Circuits

The switching time in digital circuits can be represented as a function of the power supplied, i.e., the higher the circuit speed required, the higher this power has to be.

As a rule, a switching circuit must have a certain minimum speed. This is ensured by supplying a higher power than normally required even in the nominal case (nominal voltage or current), since potential circuit and power supply tolerances have to be considered when determining the nominal values.

A regulator, arranged on or in the neighbourhood of the semiconductor chip and compensating at least the variations in the power supply, has proved an asset in some cases. However, in monolithic technology the problem is to provide a suitable voltage or current normal. A stable on-chip voltage normal is generally very difficult to obtain. External voltage normals, although being parallely distributable, are subject to series voltage drops, whereas current normals cannot be parallely distributed.

In summary, it can be said that existing solutions of the problem - guaranteed minimum speed at minimum power dissipation - are unsatisfactory, because of the high tolerances in the normals and components of the control circuit.

It is proposed, therefore, that for controlling the supplied power the value to be guaranteed (switching delay, i.e., time) be compared with an adequate normal (frequency, i.e., time), thus considerably reducing control or regulating tolerances. Moreover, the normal (external clock frequency) can be distributed parallel to the various circuit points, without being negatively affected.

An embodiment is shown schematic...