Browse Prior Art Database

Program Debugging System

IP.com Disclosure Number: IPCOM000080468D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 7 page(s) / 98K

Publishing Venue

IBM

Related People

Flanagan, HW: AUTHOR

Abstract

Described is CPU hardware intended to support the debugging of programs written in higher level languages such as FORTRAN, PL/1, COBOL, etc. This hardware is justified in those situations where debugging must be carried out in source language terms, without degrading online system performance. Online maintenance of source code in higher level languages is often preferred over maintenance of the corresponding object code in machine language. DESCRIPTION:

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Program Debugging System

Described is CPU hardware intended to support the debugging of programs written in higher level languages such as FORTRAN, PL/1, COBOL, etc. This hardware is justified in those situations where debugging must be carried out in source language terms, without degrading online system performance. Online maintenance of source code in higher level languages is often preferred over maintenance of the corresponding object code in machine language. DESCRIPTION:

The hardware system described herein consists of an assemblage of registers, control blocks, special CPU instructions, a special hardware mode for the system called "debug mode", a module-name field in the program status word (PSW), and finally a control method by which the hardware makes use of these elements to provide a source language debug capability, that is superior to an analogous capability implemented in software alone. The superiority is in efficiency of execution, and increased simplicity for the supporting software that would otherwise be required. The executing efficiency of this scheme is due to the implementation in hardware of those components of the debug function which would be most inefficient if in software, yet necessary. This system provides:
1) Continuous scrutiny of its input code in order to detect the

execution of specified debug points,
2) Identification of the various debug points that occur,
3) Automatic counting, and
4) Automatic data collection and buffer management.

The tables and control blocks herein described are assumed to have been set up by software initialization upon receipt of a debug request from the external user, prior to the actual execution of the module(s) to be debugged.

This system allows a user to identify the critical debug points by specifying (1) module name, and (2) source language statement serial number as the two coordinates of each critical debug point.

It allows the hardware to:
1) Automatically trap the occurrence of the specified debug

points,
2) Discriminate among the specified debug points, and
3) Carry out certain kinds of debug actions when the critical

debug points are trapped.

The basic kinds of debug actions that the hardware may carry out

are:
1) Augment a counter associated with the execution of the

debug point, and/or
2) Collect background data which exists when the debug

point is executed, and/or
3) Execute a "debugging program" prior to returning in-line

after the debug point.

CONTROL BLOCKS.

1

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Certain control blocks together with two control registers, regulate the action of the debug system on the occurrence of changes in the module name field of the PSW, and also on the occurrence of FLOW instructions in the instruction stream. These are: 1. The DMOD table, 2. The IPD control block, 3. The IPD process block, and 4. The IPD collector block. where IPD stands for Inter Process Debug, and DMOD stands for module debug. DMOD Table (Fig. 2):

The DMOD table (module debug table)...