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Data Store with Internal Data Transfer

IP.com Disclosure Number: IPCOM000080470D
Original Publication Date: 1973-Dec-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

East, DG: AUTHOR

Abstract

The drawing shows a representative storage cell 2 of a rectangular storage array. Representative lines 3 and 4 traverse the rows of the array and are interconnected to each storage cell along the associated row. The storage cells of a row form a bit position of the array. A storage array. Representative lines 3 and 4 traverse the rows of the array and are interconnected to each storage cell along the associated row. The storage cells of a row form a bit position of the array. A bit of a word to be stored in the array is received on a line 8 and the corresponding bit read from the array appears on a line 9. Representative lines 6 and 7 traverse the columns of the array and are connected to each cell along the associated column. A column of cells forms a storage word location.

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Data Store with Internal Data Transfer

The drawing shows a representative storage cell 2 of a rectangular storage array. Representative lines 3 and 4 traverse the rows of the array and are interconnected to each storage cell along the associated row. The storage cells of a row form a bit position of the array. A storage array. Representative lines 3 and 4 traverse the rows of the array and are interconnected to each storage cell along the associated row. The storage cells of a row form a bit position of the array. A bit of a word to be stored in the array is received on a line 8 and the corresponding bit read from the array appears on a line 9. Representative lines 6 and 7 traverse the columns of the array and are connected to each cell along the associated column. A column of cells forms a storage word location.

Line 7 receives a signal Read Select from conventional addressing circuits, not shown, to select the cells of a particular word location for a read operation, and line 6 similarly receives a signal Write Select from conventional addressing circuits for a write operation. Separate addressing circuits are provided for read and write, and is selected for a write operation, data is transferred internally from the first word location to the second word location.

Each row of the array has a circuit 12 that gates the signal Data In on line 8 to line 3 and gates a signal on line 3 to line 4. A gate 13 transfers the signal Data In to line 3 in response to a signal Data Select on a line 10. A gate 14 gates the signal on line 3 to line 4 in response to a signal Write on a line 15.

In the stora...